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RM0008
Table 64.
Analog-to-digital converter (ADC)
External trigger for regular channels for ADC3
Source
TIM3_CC1 event
TIM2_CC3 event
TIM1_CC3 event
TIM8_CC1 event
TIM8_TRGO event
TIM5_CC1 event
TIM5_CC3 event
SWSTART
Connection type
Internal signal from on-chip
timers
Software control bit
000
001
010
011
100
101
110
111
EXTSEL[2:0]
Table 65.
External trigger for injected channels for ADC3
Source
TIM1_TRGO event
TIM1_CC4 event
TIM4_CC3 event
TIM8_CC2 event
TIM8_CC4 event
TIM5_TRGO event
TIM5_CC4 event
JSWSTART
Connection type
Internal signal from on-chip
timers
Software control bit
000
001
010
011
100
101
110
111
JEXTSEL[2:0]
The software source trigger events can be generated by setting a bit in a register
(SWSTART and JSWSTART in ADC_CR2).
A regular group conversion can be interrupted by an injected trigger.
11.8
Note:
DMA request
Since converted regular channels value are stored in a unique data register, it is necessary
to use DMA for conversion of more than one regular channel. This avoids the loss of data
already stored in the ADC_DR register.
Only the end of conversion of a regular channel generates a DMA request, which allows the
transfer of its converted data from the ADC_DR register to the destination location selected
by the user.
Only ADC1 and ADC3 have this DMA capability. ADC2-converted data can be transferred in
dual ADC mode using DMA thanks to master ADC1.
Doc ID 13902 Rev 9
209/995
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